A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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IR-drop management in the power supply network of a chip is one of the critical design challenges in nanometer VLSI circuits. Techniques developed for application-specific integrated circuits cannot be directly applied for IR drop management in field-programmable gate arrays (FPGAs) because of the programmable nature of FPGAs. This paper proposes a novel clustering technique for improving the supply voltage profile in power grid of FPGAs. The proposed clustering technique not only improves the minimum voltage at any node in the circuit, but also reduces the variance in supply voltage across the nodes in the power grid. Results indicate that a reduction of up to 36% in IR-drop and 27% in spatial Vdd variation can be achieved using the proposed clustering technique.