A methodology for power-aware transaction-level models of systems-on-chip using UPF standard concepts

Authors:
Ons Mbarek;Alain Pegatoquet;Michel Auguin
Affiliations:
LEAT, University of Nice-Sophia Antipolis, CNRS, Valbonne, France;LEAT, University of Nice-Sophia Antipolis, CNRS, Valbonne, France;LEAT, University of Nice-Sophia Antipolis, CNRS, Valbonne, France
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

Building efficient and correct system power management strategies relies on efficient power architecture decision-making as well as respecting structural dependencies induced by such architecture. Transaction Level Modeling allows a rapid exploration, verification and evaluation of alternative power management architectures and strategies. This paper introduces an efficient methodology for making system power decisions at Transaction-Level (TL) by adding and verifying power intent and management capabilities into TL-models. A generic framework that abstracts relevant concepts of the IEEE 1801 (UPF) standard and implements assertion-based contracts is used throughout the methodology. A TL-model example is considered to validate the methodology.