Early Embedded Software Design Space Exploration Using UML-Based Estimation
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Model driven engineering for MPSOC design space exploration
Proceedings of the 20th annual conference on Integrated circuits and systems design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Model Driven High-Level Power Estimation of Embedded Operating Systems Communication Services
ICESS '09 Proceedings of the 2009 International Conference on Embedded Software and Systems
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
| Hi-index | 0.00 |
Defining low power design intent for a system-on-chip (SoC) consists in specifying its power management architecture and strategy according to specific low power techniques such as power gating and multi-voltage scaling requirements. Choosing the most-energy efficient power intent for a final system contributes widely to reduce its overall power consumption. At Transaction-Level, a rapid exploration of different power intent alternatives can be made. In this paper, we present a Model Driven Engineering (MDE) approach to automate low power design intent specifications and accelerate Low Power Design Intent Space Exploration (LPDISE) using a Transaction-Level power-aware design methodology. This MDE approach mainly relies on a high level abstraction of the Unified Power Format (UPF) standard concepts that fit a TLM approach use. Then, the MDE approach is applied to automatically generate a UPF code defining the most energy-efficient power intent and being a reference file for Register Transfer Level (RTL) design team. This task focuses on a smart deduction of adequate UPF commands from the high level abstraction semantics. The effectiveness of the proposed MDE approach is illustrated by an example.