Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Verification strategy for integration 3G baseband SoC
Proceedings of the 40th annual Design Automation Conference
Automated clock inference for stream function-based system level specifications
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
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During various stages of hardware design, different types of control signals get introduced; clock, reset are specified and connected at the RTL stage whereas signals like scan enable, isolation enable, power switch enable get added to implemented devices later in the flow. The quality of Top Level Control Signals (TLCS) has a direct impact on the quality of static verification which is used to verify the intended connectivity and functionality of fan-out networks corresponding to TLCS. Typically, users need to specify these TLCS (along with their intended types) for such static verification. But when TLCS are not known to the verification engineer, reverse-engineering of clock, reset and scan network implemented in a design becomes a non-trivial task. This paper proposes a framework to automatically generate a list of TLCS pertaining to the implemented design. The framework describes a heuristic-based analysis of fan-in cones, traversing backwards from the leaf cell instance pins. It is independent of design style(s) as its core strength lies in its capability to dynamically adapt to the new discoveries of the design elements made during the traversal.