Design of a low-energy data processing architecture for WSN nodes

Authors:
Cedric Walravens;Wim Dehaene
Affiliations:
K.U.Leuven ESAT-MICAS, Heverlee, Belgium;K.U.Leuven ESAT-MICAS, Heverlee, Belgium
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 7
Cited 0

Scans as Primitive Parallel Operations

IEEE Transactions on Computers
Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs

Communications of the ACM
An ultra low-power processor for sensor networks

ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
TinyBench: The Case For A Standardized Benchmark Suite for TinyOS Based Wireless Sensor Network Devices

LCN '04 Proceedings of the 29th Annual IEEE International Conference on Local Computer Networks
Computer Architecture, Fourth Edition: A Quantitative Approach

Computer Architecture, Fourth Edition: A Quantitative Approach
ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models

Proceedings of the 46th Annual Design Automation Conference
Parallel prefix (scan) algorithms for MPI

EuroPVM/MPI'06 Proceedings of the 13th European PVM/MPI User's Group conference on Recent advances in parallel virtual machine and message passing interface

Quantified Score

Hi-index	0.00

Visualization

Abstract

Wireless sensor nodes require low-energy components given their limited energy supply from batteries or scavenging. Currently, they are designed around off-the-shelf low-power microcontrollers for on-the-node processing. However, by employing more appropriate hardware, the energy consumption can be significantly reduced. This paper identifies that many WSN applications employ algorithms which can be solved by using parallel prefix-sums. Therefore, an alternative architecture is proposed to calculated them energy-efficiently. It consists of several parallel processing elements (PEs) structured as a folded tree. Profiling SystemC models of the design with ActivaSC helps to improve data-locality. Measurements of the fabricated chip confirm an improvement of 10-20x in terms of energy as compared with traditional MCUs found in sensor nodes.