Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FlexPath NP: a network processor concept with application-driven flexible processing paths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Beyond best effort: router architectures for the differentiated services of tomorrow's Internet
IEEE Communications Magazine
Wide-area Internet traffic patterns and characteristics
IEEE Network: The Magazine of Global Internetworking
A processing path dispatcher in network processor MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Instruction set architectural guidelines for embedded packet-processing engines
Journal of Systems Architecture: the EUROMICRO Journal
Queueing model analysis and scheduling strategy for embedded multi-core SoC based on task priority
Computers and Electrical Engineering
Hi-index | 0.00 |
This paper presents results of a simulated performance evaluation of RISC-based SoC platforms for networking applications and compares them to measurement results on an FPGA prototype. We use our SystemC simulation environment, which is calibrated with a reference implementation. Starting with an analysis of the reference scenario, two approaches for improvements are investigated: at first, hardware assists are added, which offload the CPU from compute-intensive bit-level manipulations. Secondly, the concept of flexible processing paths as proposed in FlexPath NP with AutoRoute is evaluated, in which certain parts of the traffic can bypass the central CPU cluster. For each of the three scenarios we determine the maximum throughput and discuss the improvements and limitations of each solution. It can be shown that a FlexPath NP may achieve up to 2.5 times the throughput of the reference scenario. Simulation results are compared to additional measurements on the FPGA platform, which led to a further refinement of our system model. The investigations provide a deeper insight on the practical benefits and limitations of system-level performance simulations.