A processing path dispatcher in network processor MPSoCs

Authors:
Rainer Ohlendorf;Michael Meitinger;Thomas Wild;Andreas Herkersdorf
Affiliations:
Technische Universität München, Institute for Integrated Systems, Munich, Germany;Technische Universität München, Institute for Integrated Systems, Munich, Germany;Technische Universität München, Institute for Integrated Systems, Munich, Germany;Technische Universität München, Institute for Integrated Systems, Munich, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

Multi-field packet classification problems discussed in the literature are typically constrained to the Internet five-tuple and primarily address the problem of network quality-of-service (QoS) support and access control. In this paper, we present a solution for a classification problem that is used for optimized packet assignment to different data paths within a network processor system-on-chip (SoC). In contrast to the five-tuple-based rules discussed in the prior art, our problem has rules that consider a larger set of fields from the packet header. However, for each individual rule a different sub-set of fields is relevant and the number of rules is smaller. Based on a specification of the usage case for our classifier we derive heterogeneous decision graph algorithm (HDGA), a heuristic approach to construct a decision tree classifier that integrates external lookup results for certain types of rules. We evaluate various parameters for optimizing the proposed decision tree and present simulation results to show the scalability of HDGA for typical problem sizes. This paper is concluded with the results of an implementation on our field-programmable gate-array (FPGA)-based prototyping platform.