System Design with SystemC
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction level modeling in practice: motivation and introduction
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Standards are emerging in the System Level Design area. After an initial period where models were created by a reduced number of experts, the trend is now to integrate models coming from various sources. In order to reduce integration effort when creating virtual prototypes, standards have been defined to increase model to model, and model to tool interoperability. After presenting the rationale for defining standards, and introducing the languages used in the field, we give a status of the currently available standards for System on Chip modeling and virtual prototype integration. We also identify the next steps, and indicate the next topics to be standardized, from a user perspective.