System level performance estimation of multi-processing, multi-threading SoC architectures for networking applications

Authors:
Nuria Pazos;Winthir Brunnbauer;Jürgen Foag;Thomas Wild
Affiliations:
Institute for Integrated Circuits, TU-Munich, Germany;Infineon, System Architecture, Data Comm., San Jose, CA;Institute for Integrated Circuits, TU-Munich, Germany;Institute for Integrated Circuits, TU-Munich, Germany
Venue:
SystemC
Year:
2003

Citing 0
Cited 2

Transaction level modeling: an overview

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The design of emerging networking architectures opens a multiple scenario of alternatives. If the design starts at a higher level of abstraction the process towards the selection of the optimal target architecture, as well as the partitioning of the functionalities, can be considerably accelerated. The present work introduces a novel system level performance estimation methodology based on SystemC. It will be shown that the rebuilding effort is considerably lower when applying the proposed methodology rather than building up a structural model of the target architecture at a lower level of abstraction. It makes feasible the exploration of several partitioning alternatives of a system specification onto a target architecture.