System Design with SystemC
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
SystemC: methodologies and applications
SystemC: methodologies and applications
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reusable component IP design using refinement-based design environment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Writing Testbenches using SystemVerilog
Writing Testbenches using SystemVerilog
EURASIP Journal on Embedded Systems
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We propose a flexible mixed-level virtual prototyping environment, where models in different abstraction levels such as transaction level, register-transfer level, and software level can be co-simulated together. In the proposed environment, the designers should capture a transaction level system model before hardware-software partitioning, from which mixed-level virtual prototyping models can be refined with pre-defined and pre-verified communication primitives. We explain several techniques employed in the environment such as ID ports for software template efficiency, abstraction adapters in SystemC for mixed level simulation, and trace-driven simulation for faster performance evaluation. Moreover, transaction level descriptions in SystemC can be compiled and executed as software together with the DEOS, which is an operating system that provides SystemC APIs. We compared the simulation speed of several mixed-level virtual prototypes of a H.264 decoder to show the effectiveness of the proposed environment.