A timing-accurate modeling and simulation environment for networked embedded systems
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ISCC '99 Proceedings of the The Fourth IEEE Symposium on Computers and Communications
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ACM SIGCOMM Computer Communication Review
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Proceedings of the conference on Design, automation and test in Europe - Volume 3
MoteLab: a wireless sensor network testbed
IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
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Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
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ATEC '04 Proceedings of the annual conference on USENIX Annual Technical Conference
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Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
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WOSP '08 Proceedings of the 7th international workshop on Software and performance
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
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HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
INFOCOM'10 Proceedings of the 29th conference on Information communications
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
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In this paper, we present the design and implementation of a general, flexible, hardware-aware network platform that takes hardware processing behavior into consideration to accurately evaluate network performance. The platform adopts a network-hardware co-simulation approach in which the NS-2 network simulator supervises the network-wide traffic flow and the SystemC hardware simulator simulates the underlying hard-ware processing in network nodes. In addition, as a case study, we implemented wireless all-to-all broadcasting with network coding on the platform. We analyze the hardware processing behavior during the algorithm execution and evaluate the overall performance of the algorithm. Our experimental results demonstrate that hardware processing can have a significant impact on the algorithm performance and hence should be taken into consideration in the algorithm design. We expect that this hardware-aware platform will become a very useful tool for more accurate network simulations and more efficient design space exploration of processing-intensive applications.