Static timing analysis of embedded software on advanced processor architectures
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Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Embedded Computing Systems (TECS)
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UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative performance analysis is not adequately taken into account in early design stages of the system. In this paper, we present our approach for formal and simulation based performance analysis of systems specified with UML2/SysML. The basis of our analysis approach is the detection of communication that synchronize the control flow of the corresponding instances of the system and make the relationship explicit. Using this knowledge, we are able to determine a global timing behavior and violations of this effected by preset constraints. Hence, it is also possible to detect potential conflicts on shared communication resources if a specification of the target architecture is given. With these information it is possible to evaluate system models at an early design stage.