Optimal VLSI Sorting with Reduced Number of Processors

  • Authors:
  • Hussein M. Alnuweiri;V. K. Prasanna Kumar

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1991

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Abstract

A new parallel architecture is presented which has p processors and N=n/sup 2/ memory locations, each consisting of 2s bits. The proposed organization can sort N s-bit numbers, where s=O((1+ epsilon ) log N), epsilon