An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Analog Device-Level Layout Automation
Analog Device-Level Layout Automation
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Symmetry-aware placement with transitive closure graphs for analog layout design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a solution to handling complex multi-group symmetry constraints in the placement design using transitive closure graph (TCG) representation for analog layouts. We propose a set of symmetric-feasible conditions, which can automatically satisfy symmetry requirements. We also develop a new contour-based packing scheme with time complexity of O(g·n·lgn), where g is the number of symmetry groups and n is the number of the placed cells. Furthermore, we devise a set of perturbation operations with time complexity of O(n). Our experimental results show the effectiveness and superiority of this proposed scheme compared to the other state-of-the-art placement algorithms for analog layout design.