An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Design Challenges of Technology Scaling
IEEE Micro
Multiple Objective Optimization with Vector Evaluated Genetic Algorithms
Proceedings of the 1st International Conference on Genetic Algorithms
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A matrix synthesis approach to thermal placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With microprocessor power densities escalating rapidly as technology scales below 100nm level, there is an urgent need for developing innovative cooling solutions. In this paper, we introduce the concept of power-density aware thermal floorplanning and demonstrate its efficacy in reducing maximum on-chip temperature. We argue that Compact Thermal Model (CTM) based floorplanners will be hard pressed by time-to-market pressure for placing circuits having large number of modules. To circumvent this problem, we present a novel power-density aware floorplanning technique for reducing the maximum on-chip temperature that has much less runtime compared to CTM based floorplanners. Based on our method we develop a floorplanner that we name COOLER. Instead of using the conventional Simulated Annealing procedure, COOLER uses a highly efficient Multiobjective Evolutionary Algorithm to generate the Pareto-front. Experimental results on MCNC benchmark demonstrate that COOLER is 11x-146x faster than HOTFLOORPLAN. We use HOTSPOT for thermal simulation of the layouts produced by COOLER. Finally, we validate our method by demonstrating that HOTFLOORPLAN solutions lie on the Pareto-front generated by COOLER. It was found that by careful arrangement of components at the architecture level, the average reduction in peak temperature produced by HOTFLOORPLAN and COOLER was 15.1°C and 15.3°C respectively.