Simultaneous placement and module optimization of analog IC's
DAC '94 Proceedings of the 31st annual Design Automation Conference
An approach to realistic fault prediction and layout design for testability in analog circuits
Proceedings of the conference on Design, automation and test in Europe
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
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This paper presents a performance-driven placement algorithm for automatic layout generation of analog IC's. The main innovations of our approach are essentially: (i) an integrated Place&Route optimization algorithm which is able to provide a realistic measurement of the interconnect parasitics, that is a key issue in performance-driven approaches; and (ii) the simultaneous consideration in the cost function of two levels of symmetries: global symmetry with respect to virtual axes and local symmetry affecting groups of cells. The flexibility and efficiency of the algorithm is mainly due to the use of the same slicing-tree representation for placement and global routing, and to the heuristic algorithm we propose for the global routing estimate. The feasibility of the proposed approach has been demonstrated with several practical examples.