Zeus: A hardware description language for VLSI
DAC '83 Proceedings of the 20th Design Automation Conference
ADL: An algorithmic design language for integrated circuit synthesis
DAC '84 Proceedings of the 21st Design Automation Conference
The icewater language and interpreter
DAC '84 Proceedings of the 21st Design Automation Conference
ALI: A procedural language to describe VLSI layouts
DAC '82 Proceedings of the 19th Design Automation Conference
SILT: a VLSI design language
Yale user''s guide: a SILT-based layout editor
Yale user''s guide: a SILT-based layout editor
A language processor and a sample language.
A language processor and a sample language.
Analog circuits optimization based on evolutionary computation techniques
Integration, the VLSI Journal
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
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This paper describes Layla, a Pascal-based hardware description language for the specification of VLSI layouts. The primary application of Layla is the development of parameterized cell libraries. Important features include Pascal's computational power and file I/O facilities, hierarchical (cell-based) layout generation, a run-time design parameter file, an extendible layer set, external compilation, the ability to support different output formats, and the automatic generation of parameterized Layla from artwork.