B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2004 international symposium on Physical design
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
Proceedings of the 2005 international symposium on Physical design
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Satisfying whitespace requirements in top-down placement
Proceedings of the 2006 international symposium on Physical design
Dragon2006: blockage-aware congestion-controlling mixed-size placer
Proceedings of the 2006 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Mixed block placement via fractional cut recursive bisection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the decreasing significance of large standard cells in technology mapping
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Constraint graph-based macro placement for modern mixed-size circuit designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Handling complexities in modern large-scale mixed-size placement
Proceedings of the 46th Annual Design Automation Conference
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In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient, effective, and flexible for handling macro placement with various constraints. Given a global placement, our MP-tree-based macro placer optimizes macro positions, minimizes the macro displacement from the initial macro positions, and maximizes the area of the chip center for standard-cell placement and routing. Experiments based on the eight ISPD'06 placement contest benchmarks show that our macro placer combined with Capo 10.2, NTUplace3, or mPL6 for standard-cell placement outperforms these state-of-the-art academic mixed-size placers alone by large margins in both robustness and quality. In addition to wirelength, experimented on five real industrial designs show that our method significantly reduce the average HPWL by 35%, the average routed wirelength by 55%, and the routing overflows than the counterpart with Capo 10.2, implying that our macro placer leads to much higher routability.