Introduction to operations research, 4th ed.
Introduction to operations research, 4th ed.
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
MOSIS: IC Prototyping and Low Volume Production Service
MSE '01 Proceedings of the 2001 International Conference on Microelectronic Systems Education (MSE'01)
Multi-project reticle floorplanning and wafer dicing
Proceedings of the 2004 international symposium on Physical design
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Chips on wafers, or packing rectangles into grids
Computational Geometry: Theory and Applications - Special issue on the 19th European workshop on computational geometry - EuroCG 03
A Comparative Study on Dicing of Multiple Project Wafers
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design space exploration for minimizing multi-project wafer production cost
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
CMP aware shuttle mask floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Shuttle mask floorplanning with modified alpha-restricted grid
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Variable-sized object packing and its applications to instruction cache design
Computers and Electrical Engineering
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Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among chips with large-volume requirements while minimizing reticle dimensions. Our mixed-integer linear programming models with VOCO are too complex to render good solutions for large test cases. Our B*-tree with VOCO and HQ with VOCO use 16%∼ 29% fewer wafers and 8%∼ 19% less reticle area than the hierarchical quadrisection (HQ) method proposed by Kahng et al. [2005]