Efficient Algorithms for Lossless Compression of 2D/3D Images
VISUAL '99 Proceedings of the Third International Conference on Visual Information and Information Systems
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Reticle floorplanning of flexible chips for multi-project wafers
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A Comparative Study on Dicing of Multiple Project Wafers
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design space exploration for minimizing multi-project wafer production cost
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
CMP aware shuttle mask floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Shuttle mask floorplanning with modified alpha-restricted grid
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Chip placement in a reticle for multiple-project wafer fabrication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal wafer cutting in shuttle layout problems
Journal of Combinatorial Optimization
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Multi-project Wafers (MPW) are an efficient way to share the rising costs of mask tooling between multiple prototype and low production volume designs. Packing the different die images on a multi-project reticle leads to new and highly challenging floorplanning formulations, characterized by unusual constraints and complex objective functions. In this paper we study multi-project reticle floorplanning and wafer dicing problems under the prevalent side-to-side wafer dicing technology. Our contributions include practical mathematical programming algorithms and efficient heuristics based on interval-graph coloring which find side-to-side wafer dicing plans with maximum yield for a fixed multi-project reticle floorplan and given per-die maximum dicing margins. We also give novel shelf packing and simulated annealing reticle floorplanning algorithms for maximizing wafer-dicing yield. Experimental results show that our algorithms improve wafer-dicing yield significantly compared to existing industry tools and academic min-area floorplanners.