MOSIS: IC Prototyping and Low Volume Production Service
MSE '01 Proceedings of the 2001 International Conference on Microelectronic Systems Education (MSE'01)
Multi-project reticle floorplanning and wafer dicing
Proceedings of the 2004 international symposium on Physical design
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Chips on wafers, or packing rectangles into grids
Computational Geometry: Theory and Applications - Special issue on the 19th European workshop on computational geometry - EuroCG 03
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Multi-project wafer has become a low-cost avenue to gain access to more advanced process technology via amortizing mask cost among chips placed on the same reticle (called reticle floorplanning). Assuming chips have flexible dimensions, we propose a non-linear programming model for reticle floorplanning to optimize reticle area and make more chips with same width or height. The model allows co-existence of chips with fixed and flexible aspect ratios and can be solved within half an hour. For the test cases originally having few chips with same width or height, our floorplanning method achieves more than 50% reduction in wafers used. We also propose an effective dicing method that saves up to 40% of wafers.