The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
DAC '82 Proceedings of the 19th Design Automation Conference
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
PHIGURE: a parallel hierarchical global router
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Path search on rectangular floorplan
EURO-DAC '90 Proceedings of the conference on European design automation
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We present a global wiring algorithm used in a top-down physical design environment, i.e. macros are laid out only after global wiring is done, and wires are allowed to pass through macros (wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. Given a balanced slicing tree representation of the floorplan, the worst-case running time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and has been used for actual chip design. Experiments showed that the hierarchical router performs better than a flat maze type router in wireability handling, equally well in wire length, and much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger sized problems).