A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A Robust Solution to the Timing Convergence Problem in High-Performance Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Performance Driven Optimization of Network Length in Physical Placement
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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Wire capacitance models used in some synthesis tools have been based on number of fanouts. These wire capacitance models can be misleading when compared to real wiring. This discrepancy can cause synthesis tools to optimize incorrectly causing severe problems with chip level timing convergence. Designs may take longer than expected and designers may work on timing paths that are not critical thus increasing the design cycle. In sub-micron designs it is crucial to improve the timing convergence between synthesis and physical design.This paper describes several practical approaches used in timing convergence of the IBM Gekko PowerPC1 microprocessor that is used in the Nintendo Gamecube system. The impact of each approach is evaluated on the timing and size of the microprocessor.