An Adaptive Interconnect-Length Driven Placer
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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In the circuit model where outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical path may not improve the performance. Since the clock period is determined by delays of both long and short paths in the combinational circuit, gates lying in sensitizable long and short paths can be selected for resizing. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our algorithms are tested on ISCAS'85 benchmark circuits and experimental results show that the clock period can be optimized efficiently with our gate selection methods