Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Comments on "A Measure of Computational Work" and "Logical Network Cost and Entropy"
IEEE Transactions on Computers
A Formula for Ternary Network Cost
IEEE Transactions on Computers
Synthesis of Combinational Logic Using Decomposition and Probability
IEEE Transactions on Computers
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Abstract The cost, or complexity, of a switching network is defined in two ways: by its diode count and by the number of modules from a predefined set required to build it. These modules were chosen as representative of a modular diode-transistor technology. With the aid of Monte Carlo methods the following formula was obtained for the average cost, C(n, g, h), of the two-level minimal form of a 1-output combinational logical network which implements a Boolean function with g "one" vertices, h "zero" vertices, and n independent variables: where the K's are constants. Since the same formula, except for the values of the constants, was obtained for the two different definitions of cost, one hopes that it would only be necessary to change the value of the constants to use the formula with other technologies. The formula was tested on 195 computer-generated samples. The average error was found to be 15.3 percent for the diode count and 15.7 percent for the module count. With the values of the K's set for predicting average diode count, the formula was tested on 48 existing networks. The average percentage error between predicted and actual cost was found to be 32.9 percent (the higher error is possibly due to a nonrandom selection of the input codes).