Multi-FPGA partitioning method based on topological levelization

Authors:
Nabil Kerkiz;Amr Elchouemi;Don Bouldin
Affiliations:
Electrical & Computer Engineering, University of Tennessee at Knoxville, TN;Electrical & Computer Engineering, University of Tennessee at Knoxville, TN;Electrical & Computer Engineering, University of Tennessee at Knoxville, TN
Venue:
Journal of Electrical and Computer Engineering
Year:
2010

Citing 8
Cited 1

Multiple-Way Network Partitioning

IEEE Transactions on Computers
Multiple-Way Network Partitioning with Different Cost Functions

IEEE Transactions on Computers
Clustering for improved system-level functional partitioning

ISSS '95 Proceedings of the 8th international symposium on System synthesis
PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multiway FPGA partitioning by fully exploiting design hierarchy

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clustering based acyclic multi-way partitioning

Proceedings of the 13th ACM Great Lakes symposium on VLSI
Hierarchical multiway partitioning strategy with hardware emulator architecture intelligence

Hierarchical multiway partitioning strategy with hardware emulator architecture intelligence
An integrated data flow visual language and software development environment

Journal of Visual Languages and Computing

Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs

VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms.