Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy

Authors:
Hsiao-Pin Su;Allen C.-H. Wu;Youn-Long Lin
Affiliations:
Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China;Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China;Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China
Venue:
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Year:
1998

Citing 13
Cited 4

Combinatorial algorithms for integrated circuit layout

Combinatorial algorithms for integrated circuit layout
Recent directions in netlist partitioning: a survey

Integration, the VLSI Journal
Exploiting signal flow and logic dependency in standard cell placement

ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Partitioning with cone structures

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Preserving HDL synthesis hierarchy for cell placement

Proceedings of the 1997 international symposium on Physical design
Physical design: reminiscing and looking ahead

Proceedings of the 1997 international symposium on Physical design
The quarter micron challenge: intergrating physical and logic design

Proceedings of the 1997 international symposium on Physical design
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century

Proceedings of the 1997 international symposium on Physical design
The future of logic synthesis and physical design in deep-submicron process geometries

Proceedings of the 1997 international symposium on Physical design
Algorithms for VLSI Physical Design Automation

Algorithms for VLSI Physical Design Automation
Clustering and linear placement

DAC '72 Proceedings of the 9th Design Automation Workshop
The placement problem as viewed from the physics of classical mechanics

DAC '75 Proceedings of the 12th Design Automation Conference
A row-based cell placement method that utilizes circuit structural properties

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Post-routing timing optimization with routing characterization

ISPD '99 Proceedings of the 1999 international symposium on Physical design
A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Using partitioning to help convergence in the standard-cell design automation methodology

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classical floorplanning harmful?

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75K to 230K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.