Computer benchmarks
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
The OpenMP Source Code Repository
PDP '05 Proceedings of the 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Proceedings of the 41st annual Design Automation Conference
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Transparent reconfigurable acceleration for heterogeneous embedded applications
Proceedings of the conference on Design, automation and test in Europe
Evaluation of Multicore Processors for Embedded Systems by Parallel Benchmark Program Using OpenMP
IWOMP '09 Proceedings of the 5th International Workshop on OpenMP: Evolving OpenMP in an Age of Extreme Parallelism
Evolution of thread-level parallelism in desktop applications
Proceedings of the 37th annual international symposium on Computer architecture
Boosting single thread performance in mobile processors via reconfigurable acceleration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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As the number of embedded applications is increasing, the current strategy of the companies is to launch a new platform within short periods of time to execute them efficiently with low energy consumption. However, for each new platform deployment, new tool chains come along, with additional libraries, debuggers and compilers. This strategy implies high hardware redesign costs, breaks binary compatibility and results in a high overhead in the software development process. Therefore, focusing on area savings, low energy consumption, binary compatibility maintenance and mainly software productivity improvement, we propose the exploitation of Custom Reconfigurable Arrays for Multiprocessor System (CReAMS). CReAMS is composed of multiple adaptive reconfigurable systems to efficiently exploit Instruction and Thread Level Parallelism (ILP and TLP) at hardware level, in a totally transparent fashion. Assuming the same chip area of a multiprocessor platform, the proposed architecture shows a reduction of 37% in energy-delay product (EDP) on average, when running applications with different amounts of ILP and TLP.