Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model
Proceedings of the tenth international symposium on Hardware/software codesign
(Self-)reconfigurable Finite State Machines: Theory and Implementation
Proceedings of the conference on Design, automation and test in Europe
Multi Component Digital Circuit Optimization by Solving FSM Equations
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Product-term-based synthesizable embedded programmable logic cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TR-FSM: Transition-Based reconfigurable finite state machine
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A dedicated reconfigurable architecture for finite state machines
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC. This paper presents a novel unbalanced unsymmetrical reconfigurable architecture for generic FSM; Compared with commercial FPGA devices, the new architecture results in area reduction of 43% and power consumption decrease of 82%.