An accurate evaluation of routing density for symmetrical FPGAs
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A router for symmetrical FPGAs based on exact routing density evaluation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Integrated Iterative Approach to FPGA Placement
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
IEEE Transactions on Computers
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This paper presents a new performance and routability driven router for symmetrical array based field programmable gate arrays (FPGAs). The objectives of our proposed routing algorithm are two-fold: (1) improving the routability of the design (i.e., minimizing the maximum required routing channel density) and (2) improving the overall performance of the design (i.e., minimizing the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing routing algorithms