A simulation tool for dynamically reconfigurable field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
Pipeline morphing and virtual pipelines
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
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This paper presents a new approach to the simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modeling dynamic reconfiguration than previously reported simulation techniques. Our method, named Clock Morphing, is based on modeling dynamic reconfiguration via a reconfigured module clock signal, while using a dedicated signal value to indicate dynamic reconfiguration.We also discuss problems associated with the other DRL simulation techniques, describe the main principles of the proposed simulation method and evaluate its feasibility by implementing of a Clock Morphing based DRL simulation in VHDL.