Performance estimation framework for automated exploration of CPU-accelerator architectures

Authors:
Tobias Kenter;Christian Plessl;Marco Platzner;Michael Kauschke
Affiliations:
University of Paderborn, Paderborn, Germany;University of Paderborn, Paderborn, Germany;University of Paderborn, Paderborn, Germany;Intel Microprocessor Technology Lab, Braunschweig, Germany
Venue:
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2011

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Abstract

In this paper we present a fast and fully automated approach for studying the design space when interfacing reconfigurable accelerators with a CPU. Our challenge is, that a reasonable evaluation of architecture parameters requires a hardware/software partitioning that makes best use of each given architecture configuration. Therefore we developed a framework based on the LLVM infrastructure that performs this partitioning with high-level estimation of the runtime on the target architecture utilizing profiling information and code analysis. By making use of program characteristics also during the partitioning process, we improve previous results for various benchmarks and especially for growing interface latencies between CPU and accelerator.