Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Coarse grain reconfigurable architecture (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes a novel reconfigurable architecture for digital signal processing (DSP). This architecture consists of a two-level array of cells and interconnections. On the upper level, fundamental DSP operations such as multiplication and addition are mapped onto blocks of 4-bit cells. On the lower level, each cell uses a 4x4 matrix of smaller ''elements'' to perform the necessary computations. Cells also contain pipeline latches for increased throughput. The architecture features a simple VLSI implementation that combines the flexibility of memory elements with the speed of DOMINO logic. Initial prototypes have been fabricated using a modest 0.5-@mm CMOS technology. Circuit simulations of the cell in 0.25-@mm technology indicate that the design achieves a clock frequency of 200MHz.