A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure

Authors:
Simon D. Haynes;Peter Y. K. Cheung
Affiliations:
-;-
Venue:
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Year:
1998

Citing 0
Cited 5

Reconfigurable computing: a survey of systems and software

ACM Computing Surveys (CSUR)
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A Digit-Serial Structure for Reconfigurable Multipliers

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Interface specification for reconfigurable components

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Extensible multiplier-accumulator blocks for FPGAs

WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies

Quantified Score

Hi-index	0.00

Visualization

Abstract

A design for a reconfigurable multiplier array is presented. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n x 4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 25 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone.