On the design of a hardware-software architecture for acceleration of SVM's training phase

Authors:
Lázaro Bustio-Martínez;René Cumplido;José Hernández-Palancar;Claudia Feregrino-Uribe
Affiliations:
Advanced Technologies Application Center, Havana, Cuba and National Institute for Astrophysics, Optics and Electronic, Puebla, México;National Institute for Astrophysics, Optics and Electronic, Puebla, México;Advanced Technologies Application Center, Havana, Cuba;National Institute for Astrophysics, Optics and Electronic, Puebla, México
Venue:
MCPR'10 Proceedings of the 2nd Mexican conference on Pattern recognition: Advances in pattern recognition
Year:
2010

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Abstract

Support Vector Machines (SVM) is a new family of Machine Learning techniques that have been used in many areas showing remarkable results. Since training SVM scales quadratically (or worse) according of data size, it is worth to explore novel implementation approaches to speed up the execution of this type of algorithms. In this paper, a hardware-software architecture to accelerate the SVM training phase is proposed. The algorithm selected to implement the architecture is the Sequential Minimal Optimization (SMO) algorithm, which was partitioned so a General Purpose Processor (GPP) executes operations and control flow while the coprocessor executes tasks than can be performed in parallel. Experiments demonstrate that the proposed architecture can speed up SVM training phase 178.7 times compared against a software-only implementation of this algorithm.