Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
On the design of a hardware-software architecture for acceleration of SVM's training phase
MCPR'10 Proceedings of the 2nd Mexican conference on Pattern recognition: Advances in pattern recognition
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In recent years, research and development in the field of machine learning and classification techniques have gained paramount importance. The future generation of intelligent embedded devices will obviously require such classi- fiers working on-line and performing classification tasks in a variety of fields ranging from data mining to recognition tasks in image and video. Among different such techniques, Support Vector Machines (SVMs) have been found to deliver state of the art performance thus emerging as the clear winner. In this work, the Support Vector Machine Learning and Classification tasks are evaluated on embedded processor architectures and subsequent architectural modifications are proposed for performance improvement of the same.