Optimization Using Neural Networks
IEEE Transactions on Computers - Special issue on artificial neural networks
Neural networks: a systematic introduction
Neural networks: a systematic introduction
Proceedings of the 6th international workshop on Hardware/software codesign
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Off-line scheduling of a real-time system
SAC '98 Proceedings of the 1998 ACM symposium on Applied Computing
The Case for Fair Multiprocessor Scheduling
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Hardware support for real-time operating systems
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A hardware/software kernel for system on chip designs
Proceedings of the 2004 ACM symposium on Applied computing
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
The Partitioned Multiprocessor Scheduling of Deadline-Constrained Sporadic Task Systems
IEEE Transactions on Computers
A class of on-line scheduling algorithms to minimize total completion time
Operations Research Letters
On-line scheduling to minimize average completion time revisited
Operations Research Letters
Journal of Real-Time Image Processing
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Today's integrated circuit technologies allow the design of complete systems on a single chip which execute complex applications specified as a set of tasks. The tasks are managed by an Operating System whose main role consists in defining the resource allocation and the temporal scheduling. One of the main characteristics of these architectures is the heterogeneity of their execution resources which makes this scheduling complex. In this paper, we propose a neural network based model for the design of heterogeneous multiprocessor architectures scheduler. Previous works have shown that neural networks using the Hopfield model can be defined to schedule tasks on an homogeneous architecture. This approach was extended to take platform heterogeneity into account. The work presented in this paper is based on a new neural network structure using inhibitor neurons. These neurons allow to limit the number of additional neurons and the number of network re-initialisations to reach convergence. We compare our network to the classic solutions based on the Hopfield neural network. These comparisons show that the number of neurons is reduced by a factor of more than two, which reduces the time convergence. We also compare our approach in terms of number of migrations with the PFair algorithm which is known as an optimal solution in the context of homogeneous architecture. The results show that our solution significantly limit the number of task migrations. Finally, we present results in the context of heterogeneous multiprocessor architectures, which is representative of complex system-on-chip.