PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Processor Description Languages
Processor Description Languages
Parallelization Approaches for Hardware Accelerators --- Loop Unrolling Versus Loop Partitioning
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
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In this paper we present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. The main contributions of the following paper are: (1) the class of piecewise regular algorithms is extended by allowing run-time dependent conditionals, (2) a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piece-wise regular algorithms, and (3) in order to achieve highest performance,we present a speculative scheduling approach. The results are applied to an illustrative example.