An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
Proceedings of the 2003 ACM symposium on Applied computing
Schedulability-driven frame packing for multicluster distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
A rapid prototyping environment for wireless communication embedded systems
EURASIP Journal on Applied Signal Processing
Quality-driven model-based architecture synthesis for real-time embedded SoCs
Journal of Systems Architecture: the EUROMICRO Journal
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Hi-index | 0.04 |
Hardware-software cosynthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium- to large-scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the cosynthesis system, may itself be nonhierarchical or hierarchical. Traditional nonhierarchical architectures create communication and processing bottlenecks and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software cosynthesis of hierarchical heterogeneous distributed embedded system architectures from hierarchical or nonhierarchical task graphs. Our cosynthesis algorithm has the following features: 1) it supports periodic task graphs with real-time constraints, 2) it supports pipelining of task graphs, 3) it supports a heterogeneous set of processing elements and communication links, 4) it allows both sequential and concurrent modes of communication and computation, 5) it employs a combination of preemptive and nonpreemptive static scheduling, 6) it employs a new task-clustering technique suitable for hierarchical task graphs, and 7) it uses the concept of association arrays to tackle the problem of multirate tasks encountered in multimedia systems. We show how our cosynthesis algorithm can be easily extended to consider fault tolerance or low-power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a cosynthesis algorithm