Determining the Order of Processor Transactions in StaticallyScheduled Multiprocessors
Journal of VLSI Signal Processing Systems
Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
On-line scheduling of hard real-time tasks on variable voltage processor
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 11th international symposium on System synthesis
Scheduling of conditional process graphs for the synthesis of embedded systems
Proceedings of the conference on Design, automation and test in Europe
Loop Transformations for Restructuring Compilers: The Foundations
Loop Transformations for Restructuring Compilers: The Foundations
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems
Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems
A High-Performance Memory Allocator for Object-Oriented Systems
IEEE Transactions on Computers
The real-time behavior of dynamic memory management in C++
RTAS '95 Proceedings of the Real-Time Technology and Applications Symposium
Task Concurrency Management Experiment for Power-Efficient Speed-Up of Embedded MPEG4 IM1 Player
ICPP '00 Proceedings of the 2000 International Workshop on Parallel Processing
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Microprocessors & Microsystems
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In this paper we propose several system-level transformations that allow to reduce the dynamic memory requirements of complex real-time multi-media systems. We demonstrate these transformations on the protocol layer of the MPEG4 IM1-player. As a consequence, up to 20% of the global power consumption of the protocol subsystem can be eliminated, which is significant due to the programmable processor target. The entire MPEG4 description is assumed to be mapped on a heterogeneous platform combining several software processors and hard-ware accelerators.