Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems

• Authors: Filip Thoen;Francky Catthoor
• Venue: Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems
• Year: 2000

From the Publisher:The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical (r)evolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging `systems-on-a-chip' (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modeling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. Existing literature in these three domains is extensively reviewed, making this book the first to give a comprehensive overview of existing techniques. The emphasis throughout the book is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking time-to-market. The proposed `Multi-Thread Graph' (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realisticperformance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects (`timeliness'), while minimizing processor cost overhead as driven by high-level cost estimators. The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by cost estimators, selects the scheduling policy for each behavior. At the low-level, RTOS synthesis generates an application-specific scheduler for the software component. The proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints.