Proceedings of the 6th international workshop on Hardware/software codesign
On Parallelizing the Multiprocessor Scheduling Problem
IEEE Transactions on Parallel and Distributed Systems
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the ninth international symposium on Hardware/software codesign
Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems
Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems
Multi-Objective Optimization Using Evolutionary Algorithms
Multi-Objective Optimization Using Evolutionary Algorithms
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Divide-and-conquer approximation algorithms via spreading metrics
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assessing task migration impact on embedded soft real-time streaming multimedia applications
EURASIP Journal on Embedded Systems - Operating System Support for Embedded Real-Time Applications
A feedback-based approach to DVFS in data-flow applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Conventional task scheduling on real-time systems with multiple processors is notorious for its computational intractability. This problem becomes even harder when designers also have to consider other constraints such as energy consumptions. Such a multi-objective trade-off exploration is a crucial step to generating cost-efficient real-time embedded systems. Although previous task schedulers have attempted to provide fast heuristics for design space exploration, they cannot handle large systems efficiently. As today's embedded systems become increasingly larger, we need a scalable scheduler to handle this complexity. This paper presents a hierarchical scheduler that combines the graph partition and the task interleaving to tackle the trade-off exploration problem in a scalable way. Our scheduler can employ the existing flattened scheduler and significantly accelerate the design space explorations for large tasks. The speed-up of up to 2 orders of magnitude has been obtained for large task models compared to the conventional flattened scheduler.