A methodology for generating verified combinatorial circuits

  • Authors:
  • Oleg Kiselyov;Kedar N. Swadi;Walid Taha

  • Affiliations:
  • Fleet Numerical Meteorology and Oceanography Center, Monterey, CA;Rice University;Rice University

  • Venue:
  • Proceedings of the 4th ACM international conference on Embedded software
  • Year:
  • 2004

Quantified Score

Hi-index 0.02

Visualization

Abstract

High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resource-bounded languages --- such as hardware-description languages --- provide strong guarantees about the runtime behavior of computations but often lack mechanisms that allow programmers to write more structured, modular, and reusable programs. To overcome this basic tension in language design, recent work advocated the use of Resource-aware Programming (RAP) languages, which take into account the natural distinction between the development platform and the deployment platform for resource-constrained software.This paper investigates the use of RAP languages for the generation of combinatorial circuits. The key challenge that we encounter is that the RAP approach does not safely admit a mechanism to express a posteriori (post-generation) optimizations. The paper proposes and studies the use of abstract interpretation to overcome this problem. The approach is illustrated using an in-depth analysis of the Fast Fourier Transform (FFT). The generated computations are comparable to those generated by FFTW.