A Fault-Tolerant Dataflow System
Computer
A Formal Definition of Data Flow Graph Models
IEEE Transactions on Computers
Mapping data flow programs on a VLSI array of processors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
Architectural improvements for data-driven VLSI processing arrays
FPCA '89 Proceedings of the fourth international conference on Functional programming languages and computer architecture
Task allocation in data flow multiprocessors: an annotated bibliography
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Buffer Assignment Algorithms on Data Driven ASICs
IEEE Transactions on Computers
Performance Tradeoffs in Rings of Data-Driven Elements
IEEE Transactions on Computers
A Functional Data-flow Architecture Dedicated to Real-time Image Processing
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Dynamic loop pipelining in data-driven architectures
Proceedings of the 2nd conference on Computing frontiers
Data-driven regular reconfigurable arrays: design space exploration and mapping
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Design and implementation of 812: A declarative data-parallel language
Computer Languages
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The design of specialized processing array architectures, capable of executing any given arbitrary algorithm, is proposed. An approach is adopted in which the algorithm is first represented in the form of a dataflow graph and then mapped onto the specialized processor array. The processors in this array execute the operations included in the corresponding nodes (or subsets of nodes) of the dataflow graph, while regular interconnections of these elements serve as edges of the graph. To speed up the execution, the proposed array allows the generation of computation fronts and their cancellation at a later time, depending on the arriving data operands; thus it is called a data-driven array. The structure of the basic cell and its programming are examined. Some design details are presented for two selected blocks, the instruction memory and the flag array. A scheme for mapping a dataflow graph (program) onto a hexagonally connected array is described and analyzed. Two distinct performance measures-mapping efficiency and array utilization-and some performance results are discussed.