Mapping data flow programs on a VLSI array of processors

  • Authors:

  • B. Mendelson;G. M. Silberman

  • Affiliations:

  • Department of Computer Science, Technion - Israel Institute of Technology, Haifa, Israel;Department of Computer Science, Technion - Israel Institute of Technology, Haifa, Israel

  • Venue:
  • ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
  • Year:
  • 1987

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Abstract

With the advent of VLSI, relatively large processing arrays may be realized in a single VLSI chip. Such regularly structured arrays take considerably less time to design and test, and fault-tolerance can easily be introduced into them. However, only a few computational algorithms which can effectively use such regular arrays have been developed so far.We present an approach to mapping arbitrary algorithms, expressed as programs in a data flow language, onto a regular array of data-driven processors implemented by a number of VLSI chips. Each chip contains a number of processors, interconnected by a set of regular paths, and connected to processors in other similar chips to form a large array. This array is thus tailored to perform a specific computational task, as an attached processor in a larger system.The data flow program is first translated into a graph representation, the data flow graph, which is then mapped onto a finite but (theoretically) unbounded array of identical processors. Each node in the graph represents an operation which can be performed by an individual processor in the array. Therefore, the mapping operation consists of assigning nodes in the graph to processors in the array, and defining the connections between the processors according to the arcs in the graph. The last step consists of partitioning the unbounded array into a number of segments, to account for the number of processors which fit in a single VLSI chip.