Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
On process-aware 1-D standard cell design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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As the lithography continues to be the biggest challenge in 20 nm technology node, the process windows become a serious concern to handle more severe process variations for better printability and yield. The mask pattern modification that is to set the printing target as the original designed patterns under the best focus, such as OPC and SRAF, becomes insufficient. With the random space and width existing in the low level interconnect layer, a process called "retargeting" to change the original line width or space for better process windows becomes much more important and noticeable. Therefore, a study of retargeting impact on interconnect becomes a must. In this paper, we are focusing on the low level metal layer to demonstrate the retargeting impact on the delay. By the test benches that we build to enumerate all the possible changes during retargeting, we analyze the worst case scenario impact for a worry-free retargeting process. We also successfully generate a compact model to predict the retargeting impact. Experimental results verify our estimation model for the retargeting's impact on the preferred and non-preferred direction, and little error is found for our compact model.