Logic Verification of ANSI-C Code with SPIN
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Assertion-Based Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Verification of temporal properties in automotive embedded software
Proceedings of the conference on Design, automation and test in Europe
Enhanced LEON3 core for superscalar processing
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
Multicore power management: ensuring robustness via early-stage formal verification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Software verification with BLAST
SPIN'03 Proceedings of the 10th international conference on Model checking software
A decade of software model checking with SLAM
Communications of the ACM
SATABS: SAT-Based predicate abstraction for ANSI-C
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Formal Verification of Hardware / Software Power Management Strategies
VLSID '13 Proceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems
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Complex and sophisticated power management strategies are a commonplace design policies today in order to manage the power consumption of complex low power digital integrated circuits. These global power management strategies are implemented in software/firmware and are used to orchestrate the switching between power states of multiple power domains in local power controllers which resides in hardware. In this paper, we propose a methodology of verifying such global power management softwares with safety linear temporal logic (LTL) properties using bounded model checking based verification approach. We present our results on several test cases of significant complexity to demonstrate the feasibility of the proposed framework.