Symbolic Model Checking
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
PRISM 2.0: A Tool for Probabilistic Model Checking
QEST '04 Proceedings of the The Quantitative Evaluation of Systems, First International Conference
Improving Multiple-CMP Systems Using Token Coherence
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Using probabilistic model checking for dynamic power management
Formal Aspects of Computing
Formal Verification and its Impact on the Snooping versus Directory Protocol Debate
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Evaluating design tradeoffs in on-chip power management for CMPs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Thermal-aware task scheduling at the system software level
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Verification-Aware Microprocessor Design
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Model checking of global power management strategies in software with temporal logic properties
Proceedings of the 6th India Software Engineering Conference
Formal verification of architectural power intent
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management of multi-core chips: challenges and pitfalls
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Reachability Analysis of Cost-Reward Timed Automata for Energy Efficiency Scheduling
Proceedings of Programming Models and Applications on Multicores and Manycores
Formal verification of distributed dynamic thermal management
Proceedings of the International Conference on Computer-Aided Design
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Dynamic power management (DPM) is important for multicore architectures. One important challenge for multicore DPM schemes is verifying that they are both safe (cannot lead to power or thermal catastrophes) and efficient (achieve as much performance as possible without exceeding power constraints). The verification difficulty varies among designs, depending, for example, on the particular power management mechanisms utilized and the algorithms used to adjust them. However, verification effort is often not considered in the early stages of DPM scheme design, leading to proposals that can be extremely difficult to verify. To address this problem, we propose using formal verification (with probabilistic model checking) of a high-level, early-stage model of the DPM scheme. Using the model checker, we estimate the required verification effort, providing insight on how certain design parameters impact this effort. Furthermore, we supplement the verifiability results with high-level estimates of power consumption and performance, which allow us to perform a trade-off analysis between power, performance, and verification. We show that this trade-off analysis uncovers design points that are better than those that consider only power and performance.