System architecture directions for networked sensors
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Assertion-based verification turns the corner
IEEE Design & Test
Assertion-Based Design
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In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities.