An approximation algorithm for fully testable kEP-SOP networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Design methods for OR-AND-OR three-level networks are useful for exploiting the flexibility of logic blocks in many complex programmable logic devices. This paper presents T RIMIN, a fast heuristic algorithm for designing OR-AND-OR networks from sum-of-products expressions. Each output of the network realizes a sum-of-complex-terms expression, where a complex term (CT) is similar to a product-of-sums expression. TRIMIN 's objective is to lower the number of gates in the network. It first generates a set of CTs by applying factorization techniques; then, it solves a set-covering problem by using a greedy algorithm to select a subset of the CTs. The effectiveness of TRIMIN is demonstrated through experimental results.